The present invention relates to a storage control system, and more particularly to a matching control system of a main storage and a buffer storage in a vector processor.
In a prior art computer system, a copy of a main storage (hereinafter MS) is stored in a buffer storage or cache (hereinafter BS) which is constructed of faster elements than those of the MS. Therefore, processor can more rapidly access the BS.
In a multi-processing system in which a plurality of instruction processors, each having a BS, share one MS, a matching control between the MS and the BS is effected when a store operation is performed from an instruction processor to the MS, in a manner described in U.S. Pat. No. 4,056,844 (JP-B-54-40182). In this system, a front address array (hereinafter FAA) is provided in the BS separately and independently from a buffer address array (hereinafter BAA) in which an address in the MS is registered. The FAA is a management table referenced by other processors for checking the store address, and serves to rapidly perform the matching control between the MS and the BS. In U.S. Pat. No. 4,056,844, the BAA is designated as BAA-1 or BAA11, and the FAA is designated as BAA2 or BAA12.
A vector processor (hereinafter VP) is used to rapidly perform scientific and technical operations. The VP comprises a plurality of vector registers (hereinafter VR's) for holding vector data and a plurality of operation units for operating on the vector data. In many cases, an element parallel system, in which vector data to be processed by one vector instruction is divided into a plurality of groups and the operations are performed in parallel in the respective groups, is adopted. In such cases, when the VP accesses the MS, it is allocated to a plurality of requesters (which access the MS and transfer data between the MS and the VR) in parallel for the divided element groups.
For a multi-processor of a super computer comprising a plurality of VP's, a plurality of scalar processors (hereinafter SP's) for performing a scalar operation and set-up operation for the VP's a BS in each SP, and the MS shared by the VP's and the SP's, no consideration has been given, in the past, to the matching control between the MS and the BS. Accordingly, the following problem has occurred in the multi-processor of the super computer.
When the store operation is performed from the VP to the MS, if the FAA for checking the store address is provided as means for effecting the matching control between the MS and the BS, substantial decrease of throughput of a store request due to waiting for FAA retrieval is unavoidable because the VP's in parallel, issue a plurality of store requests. If a plurality of FAA's are provided to comply with the store requests of the VP's, the hardware significantly increases and the device will be occupied and dominated by the FAA's.